The present invention relates to MOS (metal oxide semiconductor) transistor circuits, particularly those having a current mirror voltage amplifier circuit.
An example of a MOS transistor circuit comprising two current mirror voltage amplifier circuits is shown in FIG. 1. A first one, shown as block 1, of the current mirror voltage amplifier circuits comprises PMOS (P-channel MOS) transistors TP1 and TP2, and NMOS (N-channel MOS) transistor TN1 and TN2. A second one, shown as block 2, of the current mirror voltage amplifier circuits comprises PMOS transistors TP3 and TP4, and NMOS transistors TN3 and TN4. Each of the MOS transistors comprises first and second main electrodes and a gate electrode.
The PMOS transistors TP1 to TP4 have their first main electrodes connected to a power supply V, and their second main electrodes connected to the first main electrodes of the NMOS transistors TN1 to TN4. The transistors TP1 and TP2 have their gate electrodes connected to each other and to the first main electrode of the transistor TN1. The transistors TP3 and TP4 have their gate electrodes connected to the first main electrode of the transistor TN3. The NMOS transistors TN1 to TN4 have their second main electrodes connected to the ground G. The transistors TN1 and TN2 have their gate electrodes. connected to the gate electrodes of the transistors TN4 and TN3, respectively. The transistors TN1 and TN4 have their gate electrodes connected to a first input signal line N5, while the transistors TN2 and TN3 have their gate electrodes connected to a second input signal line N6. The transistors TN2 and TN4 have their gate electrodes connected to a first and a second output signal lines N7 and N8.
The operation of the circuit of FIG. 1 will now be described. Initially, the input signal lines N5 and N6 are in an intermediate state, i.e., the input signals are neither at "H" nor "L" for the transistors TN1 to TN4. Assume for instance, the potential on the signal line N5 slightly rises and the potential on the signal line N6 slightly falls. In the first current mirror circuit 1 comprising the transistors TP1, TP2, TN1 and TN2, the NMOS transistor TN1 becomes slightly "ON", and the current from a node N1 to the ground G slightly increases, and the potential on the node N1 slightly falls. The PMOS transistors TP1 and TP2 become slightly ON, and a current flows to a node N2. But the NMOS transistor TN2 is in a slightly "OFF" state, so that the potential on the node N2 rises. The output signal line N7 therefore becomes "H".
In the second current mirror circuit 2 comprising the transistors TP3, TP4, TN3 and TN4, the NMOS transistor TN3 becomes slightly "OFF", and a current from a node N3 to the ground G slightly decreases, and the potential on the node N3 slightly rises. The PMOS transistors TP3 and TP4 becomes slightly "OFF", and a current flowing to a node N4 decreases. But the NMOS transistor TN4 is in a slightly "ON" state, so that the current from the node N4 to the ground G increases, and the potential on the node N4 falls. The output signal line N8 therefore becomes "L".
Thus the two current mirror circuits 1 and 2 operate independently of each other.
The above-described MOS transistor circuit has been used as a high-speed voltage amplifier circuit in a semiconductor memory device and the like. But today an amplifier circuit with even higher speed is desired.